Spec: Import from HDL

Overview

Parse simple VHDL or Verilog files and generate a schematic circuit in DigitalWorks, providing the reverse path of HDL export. Enables importing existing designs and learning HDL by seeing the graphical equivalent.

Motivation

• Students can paste textbook HDL examples and see the circuit visually.
• Existing VHDL/Verilog designs from other tools can be brought into DigitalWorks.
• Enables round-trip workflow: design in schematic → export to HDL → modify in HDL → re-import.
• Bridges the gap for users transitioning between schematic and text-based design.

Requirements

Functional Requirements

1. Verilog Import: Parse synthesizable Verilog (structural and simple behavioral).
2. VHDL Import: Parse synthesizable VHDL (structural and simple behavioral).
3. Structural Import: Direct mapping of component instantiations to DigitalWorks components.
4. Behavioral Synthesis: Convert simple assign / concurrent signal assignments to gate networks.
5. Hierarchy Preservation: Modules/entities become macros in DigitalWorks.
6. Port Mapping: Module/entity ports become circuit I/O components.
7. Auto-Layout: Imported circuits are auto-laid out (uses auto-layout engine).
8. Error Reporting: Clear error messages for unsupported constructs.
9. Partial Import: Import what can be understood; flag unsupported sections.
10. Preview: Show imported circuit preview before inserting into editor.

Supported HDL Subset

Verilog:

• Module declarations with port lists.
• Wire and reg declarations.
• Continuous assignments (assign out = a & b;).
• Gate-level primitives (and, or, not, xor, nand, nor, xnor, buf).
• Module instantiation (structural).
• Simple always @(posedge clk) for flip-flop inference.

VHDL:

• Entity/architecture declarations.
• Signal declarations.
• Concurrent signal assignments (out <= a and b;).
• Component instantiation.
• Simple process(clk) for flip-flop inference.

Not Supported (initial version)

• Generate statements (loops).
• Memory/array declarations.
• Complex behavioral code (case, if-else trees beyond basic MUX inference).
• Testbench constructs.

Non-Functional Requirements

• Parsing completes in under 5 seconds for files up to 1000 lines.
• Generated circuit is functionally equivalent to the HDL (verifiable via simulation).
• Import errors clearly indicate line number and construct that failed.

Design

Import Pipeline

HDL Source File
    → Lexer/Parser (generate AST)
    → Semantic Analysis (resolve signals, check types)
    → Netlist Extraction (structural) or Synthesis (behavioral)
    → Component Mapping (HDL primitives → DigitalWorks components)
    → Circuit Construction (create Components, Wires, Pins)
    → Auto-Layout
    → Preview / Insert into Editor

Parser Strategy

Use a recursive descent parser for the supported subset:

public interface IHdlParser
{
    HdlModule Parse(string sourceCode);
    List<ParseError> Errors { get; }
}

public class HdlModule
{
    public string Name { get; set; }
    public List<HdlPort> Ports { get; set; }
    public List<HdlSignal> InternalSignals { get; set; }
    public List<HdlAssignment> Assignments { get; set; }
    public List<HdlInstantiation> Instantiations { get; set; }
}

public class HdlAssignment
{
    public string Target { get; set; }
    public HdlExpression Expression { get; set; }  // AST of Boolean expression
}

Expression-to-Gates Synthesis

Expression AST → Gate Network

a & b           → AND gate
a | b           → OR gate
~a              → NOT gate
a ^ b           → XOR gate
a ? b : c       → MUX
(complex)       → Decompose into primitives

Import Dialog

┌─────────────────────────────────────┐
│ Import HDL                          │
├─────────────────────────────────────┤
│ File: [C:\designs\alu.v    ] [...]  │
│ Format: ● Verilog  ○ VHDL          │
│                                     │
│ Status: ✓ Parsed successfully       │
│   Modules found: 2 (alu, adder)    │
│   Warnings: 1                      │
│                                     │
│ Import as:                          │
│   ○ Flat circuit (inline all)      │
│   ● Hierarchical (macros)          │
│                                     │
│ [Preview]      [Import] [Cancel]   │
└─────────────────────────────────────┘

Implementation Tasks

1. Create DigitalWorks.Core/Import/ namespace.
2. Implement Verilog lexer and parser (supported subset).
3. Implement VHDL lexer and parser (supported subset).
4. Implement structural import (instantiation → component mapping).
5. Implement expression synthesis (assign → gate network).
6. Implement flip-flop inference from always/process blocks.
7. Implement hierarchy handling (module → macro conversion).
8. Integrate with auto-layout engine for imported circuits.
9. Create import dialog with file selection and preview.
10. Implement error reporting with line numbers and suggestions.
11. Add menu item (File → Import → VHDL/Verilog).

Risks & Open Questions

• How much behavioral Verilog/VHDL to support? (scope creep risk)
• Should unsupported constructs be black-boxed (empty macro with correct ports)?
• Third-party parser libraries vs. hand-written parser for the subset?
• How to validate that the imported circuit matches the original HDL behavior?

Priority

Medium — Enables round-trip workflows and HDL learning.