Spec: Circuit Statistics

Overview

Provide comprehensive circuit analysis statistics including gate count, critical path length, fan-in/fan-out analysis, power estimation, complexity metrics, and design rule checks. Displayed in a dedicated statistics panel.

Motivation

Understanding circuit complexity is essential for:

• Estimating real-world implementation cost (gate count → chip area).
• Identifying performance bottlenecks (critical path → maximum clock frequency).
• Detecting design issues (excessive fan-out → signal degradation).
• Comparing alternative implementations objectively.
• Academic grading (verify student designs meet constraints).

Requirements

Functional Requirements

Basic Statistics

1. Component Count: Total components by type (gates, flip-flops, I/O, macros).
2. Wire/Net Count: Total number of nets and physical wire segments.
3. Pin Count: Total I/O pins (inputs, outputs).
4. Hierarchy Depth: Maximum macro nesting level.
5. Equivalent Gate Count: Normalize all components to NAND-gate equivalents.

Timing Analysis

6. Critical Path: Longest combinational path (in gate delays) from any input to any output.
7. Maximum Clock Frequency: Derived from critical path length + flip-flop setup time.
8. Path Enumeration: List top N longest paths.
9. Slack Analysis: Per-output timing slack relative to a target frequency.

Connectivity Analysis

10. Fan-In per Gate: Maximum and average fan-in across all gates.
11. Fan-Out per Pin: Maximum and average fan-out; flag pins exceeding threshold.
12. Unconnected Pins: List all floating/unconnected pins.
13. Unused Outputs: Outputs that drive nothing.
14. Combinational Loops: Detect and report feedback loops in combinational logic.

Complexity Metrics

15. Circuit Depth: Number of logic levels from input to output.
16. Connectivity Density: Wires-per-component ratio.
17. Area Estimate: Rough chip area based on gate equivalents and routing.

Design Rule Checks (DRC)

18. Missing Connections: Pins that should be connected but aren't.
19. Fan-Out Violations: Pins driving too many loads.
20. Floating Inputs: Input pins with no driver.
21. Short Circuits: Outputs directly connected to each other without tri-state.

Non-Functional Requirements

• Statistics update in real-time as the circuit is edited (or on-demand for expensive analyses).
• Critical path analysis completes in under 2 seconds for 500-component circuits.
• Results are exportable as text/CSV for grading or documentation.

Design

Analysis Engine

public class CircuitAnalyzer
{
    public CircuitStatistics Analyze(Circuit circuit);
    public CriticalPathResult FindCriticalPath(Circuit circuit);
    public List<DesignRuleViolation> RunDRC(Circuit circuit);
    public FanOutReport AnalyzeFanOut(Circuit circuit, int maxAllowed = 10);
}

public class CircuitStatistics
{
    public Dictionary<string, int> ComponentCounts { get; set; }
    public int TotalComponents { get; set; }
    public int TotalNets { get; set; }
    public int TotalPins { get; set; }
    public int EquivalentGateCount { get; set; }
    public int HierarchyDepth { get; set; }
    public int CircuitDepth { get; set; }
    public double MaxClockFrequencyMHz { get; set; }
    public double ConnectivityDensity { get; set; }
}

public class CriticalPathResult
{
    public List<Component> Path { get; set; }
    public int TotalDelay { get; set; }  // in gate delays or ns
    public Pin StartPin { get; set; }
    public Pin EndPin { get; set; }
}

Critical Path Algorithm

1. Build DAG from circuit (components as nodes, wires as edges).
2. Topological sort (break cycles at flip-flop boundaries).
3. Longest-path algorithm (dynamic programming on topological order).
4. Track actual path for visualization.
5. Highlight critical path on canvas (red overlay).

Statistics Panel UI

┌─────────────────────────────────┐
│ Circuit Statistics          [⟳] │
├─────────────────────────────────┤
│ Components                      │
│   Gates: 24 (AND:8, OR:6, ...)  │
│   Flip-Flops: 4                 │
│   I/O Devices: 6                │
│   Total: 34                     │
│   Gate Equivalents: 52          │
│                                 │
│ Timing                          │
│   Critical Path: 7 levels       │
│   Max Frequency: ~142 MHz       │
│   [Show Critical Path]          │
│                                 │
│ Connectivity                    │
│   Nets: 48                      │
│   Max Fan-Out: 5 (pin Q2)      │
│   Unconnected: 2 ⚠             │
│                                 │
│ DRC: 2 warnings, 0 errors      │
│   [Run Full DRC]                │
└─────────────────────────────────┘

Critical Path Visualization

When "Show Critical Path" is activated:

• Components on the critical path are highlighted with a red border.
• Wires on the critical path are drawn in red with increased thickness.
• Delay annotations appear on each component along the path.

Implementation Tasks

1. Create DigitalWorks.Core/Analysis/ namespace.
2. Implement basic component/wire counting and categorization.
3. Implement equivalent gate count calculation.
4. Implement DAG construction and topological sort.
5. Implement critical path (longest path) algorithm.
6. Implement fan-in/fan-out analysis.
7. Implement Design Rule Checks (floating pins, fan-out violations, shorts).
8. Create Statistics panel UI.
9. Implement critical path visualization overlay on canvas.
10. Add CSV/text export for statistics.
11. Add real-time update mode (recalculate on circuit change).

Risks & Open Questions

• How to handle combinational loops in critical path analysis (flag as error or break arbitrarily)?
• Should gate-equivalent costs be configurable (e.g., for different technology nodes)?
• Real-time update on every edit may be expensive — threshold for deferred recalculation?
• Should statistics be visible during simulation or only during editing?

Priority

Medium — Provides objective design feedback; useful for education and optimization.