Spec: Netlist Export

Overview

Enable exporting circuit connectivity as a structured netlist in industry-standard formats (SPICE, EDIF, custom JSON) for interoperability with external simulation, synthesis, and analysis tools.

Motivation

Netlists are the universal exchange format for circuit descriptions. Exporting netlists allows:

• Simulating in SPICE for analog/mixed-signal analysis.
• Importing into PCB layout tools.
• Feeding into synthesis/optimization tools.
• Machine-readable circuit representation for custom analysis scripts.

Requirements

Functional Requirements

1. SPICE Netlist: Generate SPICE-compatible netlist (subcircuits for macros).
2. EDIF Export: IEEE EDIF 2.0.0 format for EDA tool interoperability.
3. JSON Netlist: Custom JSON format for programmatic access and custom tools.
4. Hierarchical Support: Macros export as subcircuit/cell definitions.
5. Net Naming: Use annotation labels when available; auto-generate otherwise.
6. Component Mapping: Map each component to its netlist equivalent (device model).
7. Pin Mapping: Correct pin ordering per component type's standard pinout.
8. Power/Ground Nets: VCC and GND components create named power nets.
9. Bus Expansion: Multi-bit buses expand to individual nets (bus[0], bus[1], ...).
10. Export Validation: Pre-export check for floating nets, missing connections.
11. Custom Model Library: Users can define custom SPICE models for components.

Non-Functional Requirements

• Generated SPICE netlists parse without errors in LTspice, ngspice, and HSPICE.
• EDIF output is valid per the EDIF 2.0.0 specification.
• JSON netlist is well-documented with a JSON Schema.
• Export handles circuits up to 10000 components.

Design

Netlist Data Model

public class Netlist
{
    public string Name { get; set; }
    public List<NetlistComponent> Components { get; set; }
    public List<Net> Nets { get; set; }
    public List<Port> Ports { get; set; }  // top-level I/O
    public List<Netlist> SubCircuits { get; set; }  // macro definitions
}

public class NetlistComponent
{
    public string InstanceName { get; set; }
    public string ModelName { get; set; }
    public Dictionary<string, string> PinToNetMap { get; set; }
    public Dictionary<string, string> Properties { get; set; }
}

public class Net
{
    public string Name { get; set; }
    public List<PinReference> ConnectedPins { get; set; }
}

SPICE Output Example

* DigitalWorks Netlist Export
* Circuit: half_adder.dwm

.subckt HALF_ADDER A B SUM CARRY
X1 A B net1 XOR_GATE
X2 A B CARRY AND_GATE
.ends

.subckt XOR_GATE IN1 IN2 OUT
* Internal XOR implementation
.ends

JSON Output Example

{
  "name": "half_adder",
  "ports": [
    { "name": "A", "direction": "input" },
    { "name": "B", "direction": "input" },
    { "name": "SUM", "direction": "output" },
    { "name": "CARRY", "direction": "output" }
  ],
  "components": [
    { "instance": "U1", "model": "XOR2", "pins": { "A": "A", "B": "B", "Y": "SUM" } },
    { "instance": "U2", "model": "AND2", "pins": { "A": "A", "B": "B", "Y": "CARRY" } }
  ],
  "nets": [
    { "name": "A", "pins": ["port:A", "U1:A", "U2:A"] },
    { "name": "B", "pins": ["port:B", "U1:B", "U2:B"] }
  ]
}

Export Pipeline

Circuit Model
    → Net Extraction (trace connectivity, assign net names)
    → Hierarchy Extraction (identify macro boundaries)
    → Component Mapping (DigitalWorks type → netlist model)
    → Format-Specific Writer (SPICE / EDIF / JSON)
    → Validation
    → File Output

Implementation Tasks

1. Create DigitalWorks.Core/Export/Netlist/ namespace.
2. Implement net extraction algorithm (trace all connected pins).
3. Implement net naming strategy (annotations → auto-names).
4. Implement component-to-model mapping table.
5. Implement SPICE netlist writer.
6. Implement EDIF netlist writer.
7. Implement JSON netlist writer with schema.
8. Handle macro hierarchy (subcircuit/cell definitions).
9. Add export validation (floating nets, missing connections).
10. Create export dialog UI with format selection.
11. Add menu item (File → Export → Netlist).

Risks & Open Questions

• How to handle components without SPICE equivalents (LEDs, 7-segment displays)?
• Should the SPICE export include a simulation directive (.tran, .dc)?
• EDIF complexity: is full EDIF 2.0.0 needed or is a subset sufficient?
• Should there be a netlist import counterpart (covered in separate spec)?

Priority

Medium — Enables professional EDA tool interoperability.