Spec: VHDL/Verilog Export

Overview

Enable exporting DigitalWorks circuits as synthesizable VHDL or Verilog HDL code. This bridges the gap between educational schematic design and professional FPGA/ASIC workflows.

Motivation

Students and hobbyists who learn digital logic in DigitalWorks currently have no path to take their designs into real hardware. Exporting to standard HDL formats allows:

• Programming FPGAs with circuits designed in DigitalWorks.
• Importing into professional EDA tools (Vivado, Quartus, ModelSim).
• Learning HDL syntax by examining generated code alongside schematics.

Requirements

Functional Requirements

1. VHDL Export: Generate IEEE 1076-compliant VHDL from any circuit.
2. Verilog Export: Generate IEEE 1364-2005 compliant Verilog from any circuit.
3. Hierarchical Export: Macros become separate entities/modules, maintaining hierarchy.
4. Component Mapping: Map each DigitalWorks primitive (gates, flip-flops, etc.) to equivalent HDL constructs.
5. Signal Naming: Wires/nets use user-defined annotation labels when available, otherwise auto-generated names.
6. Port Definition: Top-level circuit inputs/outputs become entity/module ports.
7. Propagation Delay Annotation: Optionally include after X ns / #X delay statements.
8. Testbench Generation: Optionally generate a testbench skeleton from the circuit's test bench configuration.
9. Export Scope: Export entire circuit or selected sub-section.
10. Validation: Pre-export check for unsupported constructs (e.g., analog components, unconnected pins).

Non-Functional Requirements

• Generated code must be readable and well-formatted with comments.
• Generated code must pass syntax validation in standard HDL tools.
• Export completes in under 5 seconds for circuits with up to 1000 components.

Design

Export Pipeline

Circuit Model → Netlist Extraction → HDL Code Generation → File Output
                                          ↓
                              Template-based generation
                              per component type

Component Mapping Table

DigitalWorks Component	VHDL	Verilog
AND Gate (N-input)	output <= i0 and i1 and ...;	assign out = i0 & i1 & ...;
OR Gate	output <= i0 or i1;	assign out = i0 | i1;
NOT Gate	output <= not input;	assign out = ~in;
D Flip-Flop	process(clk) with rising_edge	always @(posedge clk)
Memory	RAM array with address decode	reg [width-1:0] mem [0:depth-1]
Macro (sub-circuit)	Separate entity/architecture	Separate module

File Structure

• One file per module/entity (hierarchical export).
• Top-level file includes component instantiations.
• Optional single-file mode (all entities in one file).

Export Dialog

• Choose format (VHDL / Verilog / both).
• Choose output directory.
• Options: include delays, generate testbench, single vs. multi-file.
• Preview pane showing generated code.

Implementation Tasks

1. Create DigitalWorks.Core/Export/ namespace with IHdlExporter interface.
2. Implement netlist extraction from Circuit model (components, nets, ports).
3. Implement VhdlExporter with template-based code generation.
4. Implement VerilogExporter with template-based code generation.
5. Handle macro hierarchy (recursive entity/module generation).
6. Implement signal naming strategy (labels → auto-names).
7. Add pre-export validation pass.
8. Create export dialog UI with format options and preview.
9. Add testbench skeleton generation.
10. Add menu item (File → Export → VHDL/Verilog).

Risks & Open Questions

• How to handle components with no direct HDL equivalent (e.g., LEDs, 7-segment displays)?
• Should clock components map to a standard clock port or generate a clock process?
• How to handle bidirectional pins and tri-state buses in the generated HDL?
• Consider supporting SystemVerilog for modern toolchain compatibility?

Priority

High — Key differentiator connecting education to professional workflows.